Radio frequency systems often require synthesizing a wide range of frequencies, which is normally achieved by a phase locked loop (PLL). The PLL has the advantage of providing the local oscillator frequency required by the radio with an improved phase noise and over a wide frequency band.
A PLL basically outputs a synthesized frequency, i.e. a local oscillator frequency generated by a voltage controlled oscillator (VCO) having its controlling (or tuning) voltage (Vtune) driven by a feedback loop. A phase detector fed by a reference frequency fref and by a variable feedback frequency fv being the synthesized frequency fout divided by a programmable divider (1/N) provides the phase difference of those two inputs to a loop filter. This is a low pass filter that averages the phase error between fref and fv and provides the Vtune tuning voltage driving the VCO. Once the PLL is locked, the following equation arises: fout=N·fref.
Two PLL architectures are most commonly used. The first architecture uses a phase-frequency detector by means of a charge pump. This circuit provides current pulses proportional to the phase error. Then the current pulses are converted to smooth control voltage by means of a low pass filter. This architecture provides the design advantage of having a closed loop frequency response easily controlled by setting the correct charge pump gain and by setting the correct loop filter component values. It is therefore easy to design a stable charge pump PLL only by tuning the loop filter or charge pump gain. Unfortunately, the charge pump architecture suffers from non-linearities caused by the non-ability of providing zero current pulses. Moreover, the main weakness of the charge pump architecture is the non-integration of the loop filter. The filter capacitance being very large, current technologies are unable to integrate these components into silicon IC. They are therefore implemented at module or printed-circuit-board level.
In order to improve the radio integration, a second architecture can be chosen, by implementing, for example, a XOR phase detector instead of an arrangement with charge pump. This architecture implies less design workload than the charge pump PLL since the phase detector is a simple XOR gate. Furthermore, the required low pass loop filter capacitors can be about a thousand times smaller than for the charge pump PLL. Therefore, these capacitors can be easily integrated.
The loop gain of an XOR PLL is equal to Kp·KVCO/N, where Kp and KVCO are the phase detector gain and the VCO gain, respectively. A gain, as used in this document, is the ratio of a change of an output value divided by the corresponding change of an input value. Kp is a fixed number equal to VCC/π, where VCC is the supply voltage of the XOR phase detector. For a given low pass filter cut-off frequency, KVCO is then the main degree of freedom to be used to control both the bandwidth and the phase margin, i.e. the difference between the phase angle of the output signal and −2π and therefore an indication of relative stability of the PLL loop. The PLL bandwidth is an important parameter of a PLL: The lower the bandwidth, the better jitter, or phase noise in the frequency domain, of the input signal is filtered. Therefore, the target VCO gain value KVCC is usually fairly low. A wide VCO frequency range is achieved by splitting up the frequency range into a large number of frequency bands (sub-bands) that can be implemented by adding additional capacitance to the oscillator core of a VCO.
However, the VCO gain changes according to the synthesized frequency. Current technologies do not provide the ability of designing constant VCO gain over a wide frequency range. These gain variations affect the PLL frequency response, and compensating them through the loop filter component values would actually not allow to reach the same PLL bandwidth and phase margin conditions.
As an example, the PLL closed loop transfer function can imply to have a VCO gain in the range of tens of MHz: Synthesizing 1 GHz with a VCO gain of 50 MHz/V implies a VCO tuning voltage range of 20 V. Integrated radio requires such frequencies, but does not provide such high voltages. The VCO frequency range is therefore split into multiple frequency bands by adding sets of additional capacitors to the oscillator core. This is achieved by using varactors, i.e. diodes whose capacitance varies with the applied voltage. In this example, the number of frequency bands can be 100 in order to provide a Vtune voltage range of 200 mV.
The frequency synthesized by a VCO having an impedance L and a capacitance C is given by
                              ω          =                      1                                          L                ·                C                                                    ,                            (                  eq          .                                          ⁢          1                )            where C=CD+CA+CF, where CD is the capacitance due to digitally controlled varactors, CA is the capacitance due to analog controlled varactors and CF is the fixed capacitance due to layout and all the devices present. A digitally controlled varactor receives ground or supply voltage at a varactor controlling node, whereas an analog controlled varactor receives a voltage that varies with the tuning voltage.
To maximize the frequency tuning range, often desired in an application, CD+CA must be as large as possible compared to CF.
To achieve this, the number of varactors must be large and must be split into a large number of digitally controlled varactor banks (named sub-bands or frequency bands). Controlling a varactor in a digital way, i.e. applying ground or supply voltage, is the way that gives the maximum ratio of maximum to minimum capacitance. But it is impossible to design all frequency bands with the same gain. The higher the synthesized frequency, the more increases the gain. Thus, a described PLL does not have the same behaviour when synthesizing a low or a high frequency. This is due to the definition of the VCO gain:
                              K          VCO                =                                            ⅆ              ω                                      ⅆ                              V                tune                                              =                                    -                                                                    ω                    3                                    ⁢                  L                                2                                      ⁢                                          ⅆ                C                                            ⅆ                                  V                  tune                                                                                        (                  eq          .                                          ⁢          2                )                                          →                      K            VCO                          =                                            ⅆ              ω                                      ⅆ                              V                tune                                              =                                    -                                                                    ω                    3                                    ⁢                  L                                2                                      ⁢                                          ⅆ                                                      C                    A                                    ⁡                                      (                                          V                      tune                                        )                                                                              ⅆ                                  V                  tune                                                                                        (                  eq          .                                          ⁢          3                )            
The impedance L and
      ⅆ          C      A            ⅆ          V      tune      are constants in a given design, so it is clear from eq. 3 that the VCO gain increases with increasing synthesized frequency ω=2π·ƒout as the cube of the frequency. These gain variations affect the PLL frequency response, compromising stability and phase noise. Since the PLL phase noise cannot be accurately quantified, tighter phase margins cannot be achieved. Furthermore, the gain variations prevent the transient response of the PLL from being precisely predictable. Therefore, the margin for the PLL settling time and the standard deviation of the synthesizer performance cannot be lowered and therefore do not allow a better production yield and a tighter margin for a receiver line-up noise budget. Therefore, the effects of a fab change cannot be mitigated.
Use of gain variation techniques in a VCO is known in the prior art. Those techniques use a selection of the gain for each frequency band or group of frequency bands from a lookup table (LUT), thus not compensating for process and temperature variations. The VCO gain variation is not controlled and implies to design with larger phase margin and with variable PLL frequency response. This is not a robust method, a lab characterization is needed to fill up the LUT, and it does not inherently compensate for process and temperature variations.